2 Detailed Description
PPWA accumulates either periods or pulse widths of an input signal. The function is particularly useful
in applications requiring frequency multiplication or division. A channel running the PPWA function can
link to a channel running the output compare (OC) function to generate an output signal that is propor-tional
to the input signal to the PPWA channel. See Motorola Programming Note TPUPN12/ D, Output
Compare TPU Function (OC), and the examples at the end of this function note for further explanation.
The user specifies the number of accumulation periods in the parameter MAX_ COUNT. During an ac-cumulation,
the TPU updates PERIOD_ COUNT with the current number of accumulated periods. AC-CUM
is used as a software accumulator for the lower 16 bits of the period/ pulse width, and PPWA_ UB
is used for the upper eight bits. Once an accumulation is completed (PERIOD_ COUNT ³
MAX_ COUNT), the TPU updates PPWA_ LW with ACCUM and then initializes ACCUM and
PERIOD_ COUNT to zero for the next accumulation. However, the TPU does not reinitialize PPWA_ UB
to zero; the user must do so.
If desired, the user can read the current, uncompleted period/ pulse-width measurement at any time in
the parameter ACCUM. ACCUM is updated at a periodic rate of 1/( ACCUM_ RATE * (resolution of
match/ capture TCR)) and also at each high-to-low input pin transition. If a running period/ pulse-width
value is not desired, ACCUM_ RATE should be set to $FF. The accuracy of the completed period/ pulse-
width measurement, assuming the TPU can measure it, depends only on the resolution of the TCR.
PPWA can also serve as a 16-bit software period/ pulse-width accumulator with programmable accura-cy.
ACCUM can be read periodically, and the difference in values represents the accumulated time be-tween
reads. For this use, MAX_ COUNT should be set to its maximum value ($ FF) and the CPU should
periodically reset PERIOD_ COUNT to zero so that ACCUM functions as a continuous modulo-16 ac-cumulator.
PPWA has four modes of operation that are determined by the bits in the host sequence field. All four
modes are continuous in operation. Two of the modes measure pulse periods; the other two measure
pulse widths.
The following paragraphs describe each of the four modes. A detailed description of the PPWA algo-rithm,
including a state diagram, is provided for reference at the end of this document.
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2.1 Mode 0: Accumulate 24-Bit Periods, No Links
Mode 0 is selected by writing a value of% 00 to the host sequence bits. In this mode, when a channel
accumulates a programmable number of periods, it generates an interrupt request to notify the CPU.
Whenever the current accumulation exceeds 16 bits and ACCUM overflows, the TPU increments
PPWA_ UB. However, since the TPU does not reset PPWA_ UB to zero after an accumulation has com-pleted,
the CPU must do so before 2 16 counts ($ FFFF) are again collected in ACCUM in a subsequent
accumulation. Otherwise, PPWA_ UB will be incorrect for subsequent accumulations. No overflow indi-cation
is provided for the case when the sum of the periods exceeds 24 bits ($ FFFFFF).
CHANNEL_ CONTROL should be configured to detect falling edges.
2.2 Mode 1: Accumulate 16-Bit Periods, Links
Mode 1 is selected by writing a value of% 01 to the host sequence bits. In this mode, a channel accu-mulates
a programmable number of periods, then generates a link to a sequential block of up to eight
channels, and finally generates an interrupt request to notify the CPU. The sum of the periods may be
as great as 16 bits ($ FFFF). An interrupt and links are also generated if the sum of periods exceeds 16
bits. When using this mode, CHANNEL_ CONTROL should be configured to detect falling edges.
The user specifies the first channel of a block of channels to be linked in START_ LINK_ CHANNEL and
the number of channels in the block in LINK_ CHANNEL_ COUNT. The link to the channels indicated by
these parameters happens under one of two conditions: 1) when an accumulation is completed, and 2)
when an accumulation exceeds 16 bits. In the latter case, PPWA_ LW is set to zero.
2.3 Mode 2: 24-Bit Pulse Widths, No Links
Mode 2 is selected by writing a value of% 10 to the host sequence bits. In this mode, once a channel
accumulates high-time pulse widths over a programmable number of periods, it generates an interrupt
request to notify the CPU. Whenever the current accumulation exceeds 16 bits and ACCUM overflows,
the TPU increments PPWA_ UB. However, since the TPU does not reset PPWA_ UB to zero after an
accumulation has completed, the CPU must do so before 2 16 counts ($ FFFF) are again collected in AC-CUM
during a subsequent accumulation. Otherwise, PPWA_ UB will be incorrect for subsequent accu-mulations.
No overflow indication is provided for the case in which the sum of the pulse widths exceeds
24 bits ($ FFFFFF). CHANNEL_ CONTROL should be configured to detect rising edges.
2.4 Mode 3: 16-Bit Pulse Widths, Links
Mode 3 is selected by writing a value of% 11 to the host sequence bits. In this mode, once a channel
accumulates the high-time pulse widths over a programmable number of periods, it generates a link to
a sequential block of up to eight channels and an interrupt request to notify the CPU. The sum of the
pulse widths may be as great as 16 bits ($ FFFF). An interrupt and links are also generated if the sum
of pulse widths exceeds 16 bits. When using this mode, CHANNEL_ CONTROL should be configured
to detect rising edges.
The user specifies the first channel of a block of channels to be linked in START_ LINK_ CHANNEL and
the number of channels in the block in LINK_ CHANNEL_ COUNT. The link to the channels indicated by
these parameters happens under one of two conditions: 1) when an accumulation is completed, and 2)
when an accumulation exceeds 16 bits. In the latter case, PPWA_ LW is set to zero.
3 Function Code Size
Total TPU function code size determines what combination of functions can fit into a given ROM or em-ulation
memory microcode space. PPWA function code size is:
38 m instructions + 5 entries = 43 long words
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4 Function Parameters
This section provides detailed descriptions of function parameters stored in channel parameter RAM.
Figure 1
shows TPU parameter RAM address mapping. Figure 2
shows the parameter RAM assign-ment
used
by the function. In the diagrams, Y = M111, where M is
the value of the module mapping bit
(MM) in the system integration module configuration register (Y = $7 or $F).
Ñ = Not Implemented (reads as $00)
Figure 1 TPU Channel Parameter RAM CPU Address Map
W = Channel number
Figure 2 PPWA Function Parameter RAM Assignment
Channel Base Parameter Address
Number Address 0 1 2 3 4 5 6 7
0 $YFFF## 00 02 04 06 08 0A Ñ Ñ
1 $YFFF## 10 12 14 16 18 1A Ñ Ñ
2 $YFFF## 20 22 24 26 28 2A Ñ Ñ
3 $YFFF## 30 32 34 36 38 3A Ñ Ñ
4 $YFFF## 40 42 44 46 48 4A Ñ Ñ
5 $YFFF## 50 52 54 56 58 5A Ñ Ñ
6 $YFFF## 60 62 64 66 68 6A Ñ Ñ
7 $YFFF## 70 72 74 76 78 7A Ñ Ñ
8 $YFFF## 80 82 84 86 88 8A Ñ Ñ
9 $YFFF## 90 92 94 96 98 9A Ñ Ñ
10 $YFFF## A0 A2 A4 A6 A8 AA Ñ Ñ
11 $YFFF## B0 B2 B4 B6 B8 BA Ñ Ñ
12 $YFFF## C0 C2 C4 C6 C8 CA Ñ Ñ
13 $YFFF## D0 D2 D4 D6 D8 DA Ñ Ñ
14 $YFFF## E0 E2 E4 E6 E8 EA EC EE
15 $YFFF## F0 F2 F4 F6 F8 FA FC FE
1514131211109 8 7 6 5 4 3 2 1 0
$YFFFW0 START_ LINK_
CHANNEL
LINK_ CHANNEL_ C
OUNT
CHANNEL_ CONTROL
$YFFFW2 MAX_ COUNT PERIOD_ COUNT
$YFFFW4 LAST_ ACCUM
$YFFFW6 ACCUM
$YFFFW8 ACCUM_ RATE PPWA_ UB
$YFFFWA PPWA_ LW
Parameter Write Access
Written by CPU
Written by TPU
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4.1 CHANNEL_ CONTROL
CHANNEL_ CONTROL is updated by the CPU with configuration data for channel control latches prior
to initialization. This data is used to configure the initial input transition to be detected and the match/
capture TCR. The following table defines the allowable data for this parameter.
START_ LINK_ CHANNEL contains the first channel number of a block of sequential channels for linking
in modes 1 and 3. The CPU updates this parameter.
4.2 START_ LINK_ CHANNEL
LINK_ CHANNEL_ COUNT specifies how many channels are linked in modes 1 and 3. The CPU up-dates
this parameter.
4.3 LINK_ CHANNEL_ COUNT
LINK_ CHANNEL_ COUNT must be a value in the following range: 0 < LINK_ CHANNEL_ COUNT £ 8.
No range check of LINK_ CHANNEL_ COUNT is performed by the TPU. If this parameter does not meet
these limits in modes 1 and 3, the results are unpredictable.
4.4 MAX_ COUNT
MAX_ COUNT contains the number of periods over which the periods or pulse widths are accumulated.
The number of accumulation periods is limited to 255. A value of either zero or one results in the accu-mulation
of one period or pulse width. The CPU updates this parameter.
4.5 PERIOD_ COUNT
PERIOD_ COUNT contains the current number of periods over which the accumulation has accrued.
The TPU updates this parameter.
4.6 LAST_ ACCUM
LAST_ ACCUM contains the time of the last update of ACCUM by the TPU due to a low-to-high input
transition (in modes 2 and 3 only), a high-to-low input transition (in all modes), or the periodic update
mechanism (see the following discussion of ACCUM_ RATE).
4.7 ACCUM
ACCUM contains the current, uncompleted number of accumulated clock periods during the current ac-cumulation
period. The TPU updates this parameter as specified by ACCUM_ RATE.
1514131211109 8 7 6 5 4 3 2 1 0
NOT USED TBS PAC PSC
Table 1 PPWA CHANNEL_ CONTROL Options
TBS PAC PSC Action
8 7 6 5 4 3 2 1 0
1 1 Do Not Force Any State
0 0 1
0 1 0
Detect Rising Edge Ð Pulse-Width (High Time) Accumulate Detect Falling Edge Ð Period Accumulate
0 0 x x
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
1 x x x
Input Channel Capture TCR1, Match TCR1
Capture TCR1, Match TCR2 Capture TCR2, Match TCR1
Capture TCR2, Match TCR2 Do Not Change TBS
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4.8 PPWA_ UB
PPWA_ UB contains the upper eight bits of the last completed accumulation of the period or pulse width.
The weighting of the LSB of this parameter is equal to twice the weighting of the MSB of the TCR used
for capture.
PPWA_ UB is incremented by the TPU whenever ACCUM overflows. This parameter must be initialized
to zero by the CPU prior to execution of initialization and after an accumulation of greater than 16 bits.
4.9 PPWA_ LW
PPWA_ LW contains the lower word of the previous accumulation of periods or pulse widths.
NOTE
Pulses that have a duration or separation that is less than the TPU latency time
cannot be measured accurately by the PPWA function. Refer to 7 Performance
and Use of Function
for information on calculating worst-case latency.
4.10 ACCUM_ RATE
ACCUM_ RATE determines the periodic rate at which ACCUM is updated to reflect the period/ pulse
width. This parameter is significant for two reasons:
1. ACCUM_ RATE determines the periodic rate at which the PPWA channel is serviced. Conse-quently,
ACCUM_ RATE should be set to a value that does not result in a service rate exceeding
performance requirements of other time functions in the user's system. The service rate for the
PPWA channel is equal to the following:
Therefore, the maximum value ($ FF) results in the least frequent service rate.
2. ACCUM_ RATE defines the accuracy of ACCUM with respect to the current, uncompleted, pe-riod/
pulse-width accumulation. In other words, ACCUM_ RATE defines how closely ACCUM re-flects
the actual period or pulse width.
NOTE
This parameter has no effect on the accuracy of PPWA_ UB and PPWA_ LW. Only
the resolution of the capture TCR affects the completed accumulation.
For example, in using ACCUM as a 16-bit software accumulator, the pulse widths accumulate and the
CPU reads ACCUM periodically. In addition, the actual cumulative pulse width between reads is greater
than or equal to 10 ms. If ACCUM_ RATE equals $14 and the resolution of the match/ capture TCR
equals 2 ms, the error in the pulse-width accumulation calculation over the interval is less than or equal
to the error for ACCUM times two:
£ 2 * (ACCUM error)
£ 2 (20) (2 -6 * 10 seconds / 1 -2 * 10 £ + 0.80%
The service rate is 25 kHz. The error is obviously more significant if the sampling time is small; there-fore,
using ACCUM as a continuous accumulator may not be acceptable in all applications.
1
ACCUM_ RATE resolution of the match TCR ( ) × ( ) ----------------------------------------------------------------------------------------------------------------------------------
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5 Host Interface to Function
This section provides information concerning the TPU host interface to the function. Figure 3
is a TPU
address map. Detailed TPU register diagrams follow the figure. In the diagrams, Y = M111, where
M is
the value of the module mapping bit (MM) in the system integration module configuration register (Y =
$7 or $F).
Figure 3 TPU Address Map
CFS[ 4: 0] Ñ PPWA Function Number (Assigned during microcode assembly)
Address 15 87 0
$YFFE00 TPU MODULE CONFIGURATION REGISTER (TPUMCR)
$YFFE02 TEST CONFIGURATION REGISTER (TCR)
$YFFE04 DEVELOPMENT SUPPORT CONTROL REGISTER (DSCR)
$YFFE06 DEVELOPMENT SUPPORT STATUS REGISTER (DSSR)
$YFFE08 TPU INTERRUPT CONFIGURATION REGISTER (TICR)
$YFFE0A CHANNEL INTERRUPT ENABLE REGISTER (CIER)
$YFFE0C CHANNEL FUNCTION SELECTION REGISTER 0 (CFSR0)
$YFFE0E CHANNEL FUNCTION SELECTION REGISTER 1 (CFSR1)
$YFFE10 CHANNEL FUNCTION SELECTION REGISTER 2 (CFSR2)
$YFFE12 CHANNEL FUNCTION SELECTION REGISTER 3 (CFSR3)
$YFFE14 HOST SEQUENCE REGISTER 0 (HSQR0)
$YFFE16 HOST SEQUENCE REGISTER 1 (HSQR1)
$YFFE18 HOST SERVICE REQUEST REGISTER 0 (HSRR0)
$YFFE1A HOST SERVICE REQUEST REGISTER 1 (HSRR1)
$YFFE1C CHANNEL PRIORITY REGISTER 0 (CPR0)
$YFFE1E CHANNEL PRIORITY REGISTER 1 (CPR1)
$YFFE20 CHANNEL INTERRUPT STATUS REGISTER (CISR)
$YFFE22 LINK REGISTER (LR)
$YFFE24 SERVICE GRANT LATCH REGISTER (SGLR)
$YFFE26 DECODED CHANNEL NUMBER REGISTER (DCNR)
CIER Ñ Channel Interrupt Enable Register $YFFE0A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH 15 CH 14 CH 13 CH 12 CH 11 CH 10 CH 9 CH 8 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0
CH Interrupt Enable
0 Channel interrupts disabled
1 Channel interrupts enabled
CFSR[ 0: 3] Ñ Channel Function Select Registers $YFFE0C Ð $YFFE12
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFS (CH 15, 11, 7, 3) CFS (CH 14, 10, 6, 2) CFS (CH 13, 9, 5, 1) CFS (CH 12, 8, 4, 0)
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HSQR[ 0: 1] Ñ Host Sequence Registers $YFFE14 Ð $YFFE16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH 15, 7 CH 14, 6 CH 13, 5 CH 12, 4 CH 11, 3 CH 10, 2 CH 9, 1 CH 8, 0
CH Action Taken
00 Accumulate 24-bit periods, no links
01 Accumulate 16-bit periods, link to one to eight channels
10 Accumulate 24-bit pulse widths, no links
11 Accumulate 16-bit pulse widths, link to one to eight channels
HSRR[ 1: 0] Ñ Host Service Request Registers $YFFE18 Ð $YFFE1A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH 15, 7 CH 14, 6 CH 13, 5 CH 12, 4 CH 11, 3 CH 10, 2 CH 9, 1 CH 8, 0
CH Initialization
00 No Host Service (Reset Condition)
01 Not implemented
10 Initialize (Init)
11 Not implemented
CPR[ 1: 0] Ñ Channel Priority Registers $YFFE1C Ð $YFFE1E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH 15, 7 CH 14, 6 CH 13, 5 CH 12, 4 CH 11, 3 CH 10, 2 CH 9, 1 CH 8, 0
CH Channel Priority
00 Disabled
01 Low
10 Middle
11 High
CISR Ñ Channel Interrupt Status Register $YFFE20
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH 15 CH 14 CH 13 CH 12 CH 11 CH 10 CH 9 CH 8 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0
CH Interrupt Status
0 Channel interrupt not asserted
1 Channel interrupt asserted
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6 Function Configuration
The CPU configures the PPWA function as follows:
1. Writes CHANNEL_ CONTROL, MAX_ COUNT, and ACCUM_ RATE to parameter RAM;
2. Writes START_ LINK_ CHANNEL, LINK_ CHANNEL_ COUNT to parameter RAM if operating in
link mode (host sequence bits = x1);
3. Writes host sequence bits according to the mode of operation;
4. Issues an HSR% 10 for initialization; and
5. Enables channel servicing by assigning a high, middle, or low priority.
The TPU executes initialization and starts accumulating the periods or pulse widths as specified by the
host sequence bits. The CPU should monitor the HSR register until the TPU clears the service request
bits to %00 before changing any parameters or before issuing a new service request to this channel.
Whenever the TPU completes an accumulation, an interrupt request is generated, and one or more
channels may be linked, depending on the mode of operation and the parameters. If an accumulation
of greater than 16 bits occurs, the host CPU must clear PPWA_ UB to zero after reading it. (The TPU
increments this parameter when ACCUM overflows.) Since ACCUM is initialized to zero by the TPU on
completion of an accumulation, no write collision of PPWA_ UB should occur since the CPU has suffi-cient
time to write this parameter before the TPU can increment it again.
7 Performance and Use of Function
7.1 Performance
Like all TPU functions, PPWA function performance in an application is to some extent dependent upon
the service time (latency) of other active TPU channels. This is due to the operational nature of the
scheduler. When signals faster than this performance limit are applied, the PPWA function may miss
edges and produce results inconsistent with normal operation. The following sections give details to
help calculate the actual performance limits of the function, together with the likely results when these
limits are exceeded.
7.1.1 TPU Input Filtering
All TPU channels configured as inputs have an associated synchronizer and digital filter that samples
pin transitions. These filter out high and low pulse widths less than two system clocks and are only guar-anteed
to pass pulses with a period greater than four system clocks. This operation must always be
considered when operating the TPU with short duration input pulses.
7.1.2 Operational Overview
To understand the performance limitations of the PPWA function, it is necessary to know what TPU mi-crocode
is executed at what times. By calculating the time required to execute the microcode and taking
into account other TPU latency considerations, one can make an estimate of the fastest reliable oper-ation.
7.1.2.1 PPWA Operations and PPWA State Timing
To simplify the explanation of PPWA timing, this section on PPWA performance describes PPWA func-tion
in terms of the operation being performed, such as update processing, rather than in terms of the
state being executed. To enable the reader to look up the operation in the PPWA State Timing Table or
correlate the operation to the algorithm description later in this programming note, the state is also pro-vided
in parentheses.
The PPWA state timing table that follows lists the CPU clock cycles and RAM accesses for each PPWA
state, according to the operation being performed. The table is referred to in subsequent paragraphs.
The number of clock cycles listed are maximum service times, not including time slot transition times.
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7.1.2.2 Period Measurement (Modes 0 and 1)
The TPU first performs an initialization sequence after the PPWA function has been configured and en-abled
by the CPU. After initialization, the first falling edge causes the function to begin start-edge pro-cessing
(S2). Each subsequent falling edge causes period end/ start processing (S4). TPU processing
to periodically update the ACCUM parameter, at the rate set in ACCUM_ RATE, may also be performed
but is not shown.
Figure 4 Periodic Mode Timing
1. Processing of 16-bit overflow requires that S4 be executed twice. Because the microcode instructions branch
differently, depending on whether or not 16-bit overflow needs to be processed, is currently being processed, or
does not need to be processed, the number of clock cycles varies with each execution of the state. In this case,
the first and second executions of S4 require 34 and 42 clock cycles, respectively. In addition, TPU overhead
and latency must be taken into account, as well as the possibility of another channel being serviced between the
two executions of S4. Refer to 7.2 Overflow and Update Processing
to determine if these timings must be in-cluded.
2. Assumes one channel linked. Add two clocks for each additional channel linked.
3. Clock cycles/ RAM accesses shown for operation without 16-bit overflow error condition.
4. Periodic update processing occurs in state 4 on a match while the pin is low, or in state 5 on a match while the
pin is high; the timing is identical for both cases. (In the latter case, the microcode jumps to the update routine
in state 4.)
Table 2 Period/ Pulse-Width Accumulator Ñ State Timing
State PPWA Operation CPU Clock
Cycles
RAM Ac-cesses
S1 Init Initialize (All Modes) 6 2
S2 First_ H_ L Start Edge -Period Mode (Modes 0 and 1) 6 2
S3 High_ Time_ Begin Start Edge -Pulse Mode (Modes 2 and 3) 6 2
S4 Accum_ Low_ Pin Period End/ Start Mode 0
No 16-bit overflow
16-bit overflow 1
Mode 1 2,3 Pulse End
Mode 2 No 16-bit overflow
16-bit overflow 1
Mode 3 2,3
Periodic Update (on match while pin is low) 4 Mode 0
Mode 1
42
34 + 42
50
42
34 + 42
50
34
26
10
8 + 10
12
9
7 + 9
11
8
6
S5 Accum_ High_ Pin Periodic Update (on match while pin is high) 4
Modes 0 and 2 Modes 1 and 3 34
26
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TPU PPWA PERMODE TIM
INITIALIZE (S1) START EDGEÐ PERIOD MODE
(S2)
PERIOD END/ START (S4) PERIOD END/ START (S4) PERIOD END/ START (S4)
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When PPWA measures periods, it measures from falling edge to falling edge. Consequently, the input
signal limitation is the period between these edges. This limitation is shown as Limit( 1) in Figure 4.
As
long as the TPU input filter conditions are met, the duty cycle does not affect this mode of operation.
7.1.2.3 Pulse Measurement (Modes 2 and 3)
The main TPU microcode execution associated with pulse measurement is shown in Figure 5.
The TPU
first performs an initialization sequence after the PPWA function has been configured and enabled.
Af-ter
this, each rising edge initiates start-edge (S3) processing, and each falling edge initiates pulse-end
(S4) processing. TPU processing to periodically update the ACCUM total, at the rate set in
ACCUM_ RATE, may also be performed but is not shown.
Figure 5 Pulse Mode Operation
As shown in Figure 5,
when PPWA measures pulse widths, it begins edge processing with the rising
edge and completes processing
with the falling edge. Here, duty cycle does affect operation, and both
the low and high times must have a minimum duration to guarantee correct operation. These are shown
as Limit( 2) and Limit( 3) in Figure 5.
7.2 Overflow and Update Processing
As shown in the PPWA State Timing table, edges that generate 16-bit overflows result in additional pro-cessing
time during period-end and pulse-end processing. The periodic update operation also involves
additional processing time. Depending on the PPWA application, either or both of these operations
need to be taken into account when calculating maximum PPWA performance. If the PPWA function is
known to be used in such a way that periodic updates and/ or 16-bit overflows do not occur, then a higher
maximum performance can be guaranteed for the function.
If the programmed periodic update period is longer than the longest input period, then update process-ing
will never be performed and does not need to be included in performance calculations. To determine
whether overflow processing should be included, the maximum value for the accumulated periods or
pulses, PPWA_ UB/ LW, should be determined. If this value exceeds $FFFF TCR counts, then overflow
processing should be included when calculating performance limits. Note that the PPWA State Timing
table gives timings for 16-bit overflows occurring in the 24-bit modes only, as an overflow in a16-bit
mode is an error condition that does not result in a valid measurement.
7.3 Period Mode Limit Calculation
Figure 6
shows a worst-case example for period accumulation. TPU processing required is shown as
shaded areas.
The worst-case time slot latencies, shown as WCTSL, are the calculated worst case
times from the time that the PPWA channel requests service until the time that it actually begins service.
Because the period accumulation terminated by the first falling edge results in a 16-bit overflow, and a
periodic update begins service shortly before this edge, both periodic update and overflow processing
have to be completed before the next falling edge. Note that only a single worst case time slot latency
period is required during the following period. Note also that the extra overflow and update processing
determines the minimum period of the following pulse, which may or may not itself generate an overflow
or periodic updates.
TPU PPWA PLSMODE TIM
INITIALIZE (S1) START EDGEÑ PULSE MODE
(S3)
PULSE END (S4) START EDGE (S3) PULSE END (S4) START EDGE (S3)
LIMIT( 2) LIMIT( 3)
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Figure 6 Period Mode Worst Case
For period accumulation, update processing needs to be included in the minimum period/ Limit( 1) cal-culations
only if T_ Update < Max_ Period, where Max_ Period is the known maximum input period be-tween
negative edges, and T_ Update is the update period.
Following are calculations to determine Limit 1. Here, T_ Update = ACCUM_ RATE * TCR timebase.
If T_ Update < Max_ Period then
Limit( 1) = WCTSL + Period End/ Start (S4) processing time + Update (S4 or S5) processing time
Else
Limit( 1) = WCTSL + Period End/ Start (S4) processing time
The maximum possible PPWA_ UB/ LW result should be calculated to determine whether overflow pro-cessing
should be included. If the maximum PPWA_ UB/ LW is greater than $FFFF, then the Period End/
Start (S4) timings including overflows should be used in the above calculation.
7.4 Example of Period Mode Limit Calculation
In this example, PPWA is being used with the following configuration:
° 24-bit period accumulation (mode 0)
° MAX_ COUNT = 4 (accumulation of four pulses)
° TPU RAM collision rate (RCR) = 0.1. The RAM collision rate is an approximation of the percentage
of time the CPU and the TPU try to access the RAM simultaneously.
° ACCUM_ RATE = $FF
° Selected TCR period = 238.4 ns
° CPU clock speed = 16.778 MHz
° No other TPU channels operating
° Maximum input period (Max_ Period) between falling edges = 200 us.
The following calculations determine the input signal limitations (in this case, limit 1):
1. Determine if periodic updates should be included in the calculation for input signal limitations:
T_ Update = ACCUM_ RATE * TCR period = $FF * 238.4 ns = 60.792 ms
T_ Update is less than Max_ Period. Thus, periodic updates need to be included.
2. Determine if overflow processing should be included in the calculation for input signal limita-tions:
Maximum possible PPWA_ UB/ LW = MAX_ COUNT * Max_ Period = 4 * 200 ms = 800 ms
Maximum number of TCR counts = 800 ms/ 238.4 ns = $0D1C TCR counts
TPU PPWA PERWCL TIM
PERIODIC UPDATE SERVICED JUST
BEFORE NEGATIVE EDGE
BOTH PERIODIC UPDATE AND OVERFLOW TO BE PROCESSED IN THIS SAME TIME, INCLUDING
A SINGLE PERIOD OF WORST-CASE TIME SLOT LATENCY. THIS DETERMINES LIMIT( 1).
WCTSL PERIODIC UPDATE
(S5)
WCTSL PERIOD END/ START (INCL. OVERFLOW)
(S4)
PERIODIC UPDATE MATCH
PERIOD( S) RESULTING IN 16-BIT OVERFLOW
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Maximum possible accumulation count in PPWA_ UB/ LW is less than $FFFF, so overflow processing is
not required.
3. Calculate worst case latency (WCTSL):
WCTSL = time slot transition time + 4 clock NOP = 10 CPU clks + 4 CPU clks = 14 CPU clks
There is a 10-clock delay between servicing time slots. In addition, there is one four-clock NOP between
the time that all of the channels requesting service on a particular priority level are granted service and
the next time slot transition.
4. Calculate Period End/ Start (S4) processing time (Refer to the PPWA State Timing Table for the
number of clock cycles and RAM accesses).
S4 = Num of Clock Cycles + (Num of RAM Accesses * RCR * 2) = 42 + (10 * 0.1 * 2) = 44 CPU clks
5. Calculate Update (S4 or S5) processing time (Refer to the PPWA State Timing Table for the
number of clock cycles and RAM accesses):
Update Processing Time = Num of Clock Cycles + (Num of RAM accesses * RCR * 2)
= 34 + (8 * 0.1 * 2) = 35.6 CPU clks
6. Substitute previously calculated values into the calculation for the Limit( 1) input signal limita-tion:
Limit 1 = WCTSL + Period End/ Start( S4) processing time + Update (S4 or S5) processing time
= 14 + 44 + 35.6 = 93.6 CPU clocks = 5.57 ms
7.5 Pulse Mode Limit Calculation
Figure 7
and Figure 8
show the corresponding worst cases for pulse mode operation. Figure 7
shows
the worst
case timings
to determine the minimum allowable low time (limit( 2)), while Figure 8 shows
the
corresponding timings for the minimum high time (limit( 3)).
During pulse accumulation, processing is required for both rising and falling input edges, thus limiting
the minimum low and high times of the input signal. Each falling edge of the input signal must be han-dled
by pulse end processing, as shown in Figure 7
and detailed in the PPWA State Timing table. This
defines the minimum low time (limit( 2)). If the update
period is less than the maximum input high time,
Max_ High, then periodic update processing time must also be included. In the following equations,
T_ Update = ACCUM_ RATE * TCR timebase.
If T_ Update < Max_ High then
Limit( 2) = WCTSL + Pulse End (S4) processing time + Update (S5) processing time
Else
Limit( 2) = WCTSL + Pulse End (S4) processing time
Determining whether overflow processing should be included in the previous calculation requires cal-culation
of the maximum possible PPWA_ UB/ LW result. If this result is greater than $FFFF, then the
Pulse End (S4) timings including overflows should be used in the previous calculation.
Rising edges are handled by start edge (S3) processing as shown in Figure 8.
This defines the mini-mum
high time, limit( 3). Periodic update processing time must be included if the
update period is less
than the maximum period between positive edges, Max_ Period 2.
If T_ Update < Max_ Period 2 then
Limit 3 = WCTSL + Start Edge (S3) processing time + Update (S5) processing time
Else
Limit 3 = WCTSL + Start Edge (S3) processing time
As start edge (S3) processing time is unaffected by overflows in the PPWA_ UB/ LW result, overflows do
not affect limit( 3) values.
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Figure 7 PPWA Minimum Low Time
Figure 8 PPWA Minimum High Time
7.6 Example of Pulse Mode Limit Calculations
In this example, PPWA is being used with the following configuration:
° 16-bit pulse width accumulation with links (mode 3)
° PPWA links to two output compare (OC) channels
° MAX_ COUNT = 1 (accumulate one pulse width)
° TPU RAM collision rate (RCR) = 0.1
° ACCUM_ RATE = $10
° Maximum input period, Max_ Period 2, between rising edges = 100 ms
° Maximum input high time, Max_ High, = 80 ms
° selected TCR period = 238.4 ns
° PPWA operating at high priority
° 2 OC channels operating at low priority
° CPU clock speed is 16.78 MHz
The following calculations determine the input signal limitations (Limit( 2) and Limit( 3)):
1. Determine if periodic updates should be included in the Limit( 2) and Limit( 3) calculations:
T_ Update = ACCUM_ RATE * TCR timebase = $10 * 238.4 ns = 16 * 238.4 ns = 3.8144 ms
T_ Update < Max_ Period 2, and T_ Update < Max_ High. Thus, periodic updates need to be included in
both Limit( 2) and Limit( 3) calculations.
TPU PPWA PLS MINLO TIM
PERIODIC UPDATE SERVICED JUST
BEFORE NEGATIVE EDGE
BOTH PERIODIC UPDATE AND OVERFLOW TO BE PROCESSED IN THIS SAME TIME, INCLUDING
A SINGLE PERIOD OF WORST-CASE TIME SLOT LATENCY . THIS DETERMINES LIMIT( 2).
WCTSL PERIODIC UPDATE
(S5)
WCTSL PULSE END (INCL. OVERFLOW)
(S4)
PERIODIC UPDATE MATCH
PULSE( S) RESULTING IN 16-BIT OVERFLOW
TPU PPWA PLS MINHI TIM
PERIODIC UPDATE SERVICED JUST
BEFORE POSITIVE EDGE
BOTH PERIODIC UPDATE AND START EDGEÑ PULSE MODE (S3) TO BE PROCESSED IN THIS SAME TIME, INCLUDING
A SINGLE PERIOD OF WORST-CASE TIME SLOT LATENCY . THIS DETERMINES LIMIT( 3).
WCTSL PERIODIC UPDATE
(S4)
WCTSL START EDGE (S3)
"NULL" PERIODIC UPDATE MATCH
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2. No overflow processing is required in the Limit( 2) and Limit( 3) calculations, since PPWA is con-figured
in 16-bit mode.
3. Calculate the worst case time-slot latency (WCTSL). Here, it is possible for the OC function to
be serviced between two PPWA time slots. Thus, the service time for the OC function must be
included in the worst-case time-slot latency calculations along with the standard 10-clock time-slot
transition time and 4-clock NOP.
Service time for OC function = Num of clocks + (Num of RAM accesses * RCR * 2)
= 32 + (6 * 0.1 * 2) = 33.2 CPU clocks
WCTSL = TST + NOP + single OC service time + TST
= 10 CPU clks + 4 CPU clks + 33.2 CPU clks + 10 CPU clks = 57.2 CPU clks
WCTSL is determined by the number of functions running, their types and priorities. There is a 10-clock
delay between servicing time slots (shown as TST in calculation). In addition, there is one four-clock
NOP between the time that all of the channels requesting service on a particular priority level are grant-ed
service and the next time slot transition. The service time shown for the OC function is that of state
S2, Offset_ Cal, for links other than the first after initialization.
4. Calculate the pulse end (S4) processing time. Refer to the PPWA State Timing Table for the
number of clock cycles and RAM accesses. Remember that two clock cycles are added to the
value in the table for each additional channel that is linked.
S4 = clock cycles + (Num of RAM accesses * RCR * 2) = 52 + (11 * 0.1 * 2) = 54.2 CPU clks
5. Calculate the update (S5) processing time:
S5 = clock cycles + (Num of RAM accesses * RCR * 2) = 26 + (6 * 0.1 * 2) = 27.2 CPU clks
6. Calculate the start edge (S3) processing time:
S3 = clock cycles + (Num of RAM accesses * RCR * 2) = 6 + (2 * 0.1 * 2) = 6.4 CPU clks
7. Substitute these calculated values into the Limit( 2) and Limit( 3) calculations:
Limit( 2) = WCTSL + S4 + S5 = 57.2 + 54.2 + 27.2 = 138.6 CPU clocks = 8.26 ms
Limit( 3) = WCTSL + S3 + S5 = 57.2 + 6.4 + 27.2 = 90.8 CPU clocks = 5.41 ms
Minimum pulse low time is 8.26 ms, and the minimum pulse high time is 5.41 ms.
7.7 Single Fast Pulse Handling
The PPWA limits calculated above are all based on the PPWA function measuring sustained repetitive
high speed signals. Pulses or periods faster than these limits may be measured if they do not occur
repetitively, but are instead separated by pulses/ periods much slower than the calculated limits.
7.8 Typical Error Results
When the PPWA function attempts to measure input signals that do not meet the limitations, the result-ant
measurement may not be as expected. In period accumulation mode, applying a signal which has
faster periods than the minimum calculated as Limit 1 may result in edges being missed by the function.
This will result in two or more periods being recognized as a single period, as shown in Figure 9.
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Figure 9 Period Mode Error Example
In pulse accumulation mode, attempting to measure a signal with a high time less than the specified
minimum, Limit( 3), may result in the falling edge being missed. This will return a pulse measurement
from the first rising edge to the first captured falling edge as shown in Figure 10.
Figure 10 High Error Example
Attempting to measure a signal that has a low time less than Limit( 2) can have either of two results:
1. The following pulse may be missed, with no measurement made, as in Figure 11a.
2. The next measurement may be made from the falling edge at the start of the short
low time to
the next recognized falling edge, as in Figure 11b.
Extra edges may be missed if the input signal has more than one consecutive violation of a timing lim-itation.
An example is shown in Figure 11c,
where a fast high time follows a fast low time. In this case,
the falling edge after the fast high pulse is
missed, so the pulse measurement continues until the next
falling edge.
TPU PPWA HI ERR TIM
HIGH TIME > LIMIT NO ERROR HIGH TIME < LIMIT ERROR
MEASURED PULSE MEASURED
PULSE MEASURED PULSE
HIGH TIME > LIMIT NO ERROR HIGH TIME > LIMIT NO ERROR
TPU PPWA PER ERR TIM
PERIOD > LIMIT NO ERROR PERIOD > LIMIT NO ERROR PERIOD > LIMIT NO ERROR PERIOD < LIMIT ERROR
MEASURED PERIOD MEASURED PERIOD MEASURED PERIOD
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Figure 11 Low-Time Error Examples
7.9 Changing Mode
The host sequence bits are used to select PPWA function operating mode. Change host sequence bit
values only when the function is stopped or disabled (channel priority bits = %00). Disabling the channel
before changing mode avoids conditions that cause indeterminate operation.
TPU PPWA LO ERR TIM
LOW TIME > LIMIT NO ERROR LOW TIME < LIMIT ERROR
MEASURED PULSE MEASURED PULSE
LOW TIME > LIMIT NO ERROR
MISSED PULSE NO MEASUREMENT MEASURED PULSE
LOW TIME > LIMIT NO ERROR LOW TIME < LIMIT ERROR
MEASURED PULSE MEASURED PULSE
LOW TIME > LIMIT NO ERROR
MEASURED PULSE MEASURED PULSE/ PERIOD
LOW TIME > LIMIT NO ERROR
LOW TIME < LIMIT ERROR
MEASURED PULSE MEASURED PULSE
LOW TIME > LIMIT NO ERROR
MEASURED PULSE/ PERIOD
HIGH TIME < LIMIT ERROR
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8 Function Examples
8.1 Example A
8.1.1 Description
This example uses the PPWA function with the output compare (OC) function to multiply PPWA input
frequency by two. The PPWA function repeatedly accumulates one input period and then generates a
link to the OC function. The OC function scales the accumulated period and then generates the scaled
output. The PPWA function uses channel 0, and the OC function uses channel 3. Both outputs are 50%
duty cycle.
8.1.2 Initialization
The PPWA function is assigned to channel 0 so that it has higher priority than the OC function. It is set
up for mode 1, accumulate 16-bit periods with links. Its parameters are initialized as follows:
START_ LINK_ CHANNEL is set to 3, since the OC function is on channel 3.
LINK_ CHANNEL_ COUNT is set to 1, since there is one channel in the link block.
CHANNEL_ CONTROL is set to $0B. This sets the TBS field to capture and match TCR1, the PAC field
to detect falling edge for period accumulate, and the PSC field to not force any state.
MAX_ COUNT is the number of periods per accumulation. In this case it is one.
ACCUM_ RATE determines how often ACCUM is updated during accumulations. Since a running accu-mulation
is not desired, this parameter is set to the slowest rate possible, $FF.
The host sequence field bits are set to %01, accumulate 16-bit periods with links. The host service re-quest
bits are set to %10, initialization.
Load parameter RAM as shown.
The OC function is set up on channel 3 in continuous pulse mode. Its parameters are initialized as fol-lows:
CHANNEL_ CONTROL is set to $8A. This captures and matches TCR1, forces the pin low on a match,
and forces the initial pin level low. It configures the pin level response such that the input wave and out-put
wave are in phase.
RATIO is an 8-bit fractional number between 0 and $FF used to scale the value indicated by
REF_ ADDR2 to form the output pulse hightime. Here, REF_ ADDR2 points to PPWA_ LW. Thus, for the
input PPWA channel, PPWA_ LW represents a period accumulation, while for the output OC channel,
it represents the unscaled output pulse hightime. The following equation relates the accumulation value
in PPWA_ LW, the desired output period, and RATIO:
Table 3 PPWA Channel Parameter RAM
$FFFF00 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 1
$FFFF02 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
$FFFF04 X X X X X X X X X X X X X X X X
$FFFF06 X X X X X X X X X X X X X X X X
$FFFF08 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
$FFFF0A X X X X X X X X X X X X X X X X
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T o = 2 * A i * (RATIO / 255) seconds
In this equation, A i is the accumulation value in PPWA_ LW multiplied by the resolution of the timer for
the input channel, and T o is the period of the output pulse multiplied by the resolution of the timer for
the output channel. The factor of 2 is included since the OC channel scales the value in PPWA_ LW to
be the output pulse hightime instead of the output pulse period. Thus, the scaled output pulse hightime
must be multiplied by two in order to calculate the output pulse period.
Solving this equation for RATIO yields the following:
RATIO = (T o /A i ) * (255 / 2)
In this example, the desired ratio of the output period to the input period is 1/ 2. Since the value accu-mulated
in PPWA_ LW (A i )represents one input period, T o /A i is also 1/ 2. Thus, RATIO = 1/ 2 * 255/ 2 =
(approximately) 64 = $40.
REF_ ADDR1 points to a synchronization reference value used whenever a link is received that is not
the first link after initialization. Here, it points to LAST_ ACCUM.
REF_ ADDR2 points to a reference value used in calculating the output pulse hightime. Here, it points
to PPWA_ LW.
REF_ ADDR3 points to a synchronization reference value used when the first link service request is ser-viced
after initialization.
The host sequence field bits are initialized to %00, matches and pulses scheduled. The host service
request bits are set to %11, initialization for the continuous mode.
Load parameter RAM as shown.
8.2 Example B
8.2.1 Description
This example also uses the PPWA function with the OC function to multiply the PPWA input frequency
by two. In this example, however, the PPWA function repeatedly accumulates two input pulse high
times and then generates a link to the OC function. The OC function scales the accumulated high times
and then generates the scaled output. The PPWA function uses channel 0, and the OC function uses
channel 3. Both outputs are 50% duty cycle.
8.2.2 Initialization
The PPWA function is assigned to channel 0 so that it has higher priority than the OC function. It is set
up for mode 3, accumulate 16-bit pulse widths with links. Its parameters are initialized as followed:
START_ LINK_ CHANNEL is set to 3, since the OC function is on channel 3.
Table 4 OC Channel Parameter RAM
$FFFF30 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0
$FFFF32 X X X X X X X X X X X X X X X X
$FFFF34 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0
$FFFF36 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0
$FFFF38 X X X X X X X X X X X X X X X X
$FFFF3A X X X X X X X X X X X X X X X X
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LINK_ CHANNEL_ COUNT is set to 1, since there is one channel in the link block.
CHANNEL_ CONTROL is set to $07. This sets the TBS field to capture and match TCR1, the PAC field
to detect rising edge for pulse accumulation, and the PSC field to not force any state.
MAX_ COUNT is the number of pulse high times per accumulation. In this case it is two.
ACCUM_ RATE determines how often ACCUM is updated during accumulations. Since a running accu-mulation
is not desired, this parameter is set to the slowest rate possible, $FF.
The host sequence field bits are set to %11, accumulate 16-bit pulse widths with links. The host service
request bits are set to %10, initialization.
Load parameter RAM as shown.
The OC function is set up on channel 3 in continuous pulse mode. Its parameters are initialized as fol-lows:
CHANNEL_ CONTROL is set to $008A. This captures and matches TCR1, forces the pin low on a
match, and forces the initial pin level low.
RATIO is an 8-bit fractional number between 0 and $FF used to scale the value indicated by
REF_ ADDR2 to form the output pulse hightime. Here, REF_ ADDR2 points to PPWA_ LW. Thus, for the
input PPWA channel, PPWA_ LW represents a period accumulation, while for the output OC channel,
it represents the unscaled output pulse hightime. The following equation relates the input pulse hightime
accumulation in PPWA_ LW, the desired output period, and RATIO:
T o = 2 * A i * (RATIO/ 255) seconds
In this equation, A i is the accumulation value in PPWA_ LW multiplied by the resolution of the timer for
the input channel, and T o is the period of the output pulse multiplied by the resolution of the timer for
the output channel. The factor of 2 is included since the OC channel scales the value in PPWA_ LW to
be the output pulse hightime instead of the output pulse period. Thus, the scaled output pulse hightime
must be multiplied by two in order to calculate the output pulse period.
Solving this equation for RATIO yields the following:
RATIO = (T o /A i ) * (255/ 2)
In this example, the desired ratio of the output period to the input period is 1/ 2. Thus, the desired ratio
of the output period to a single input pulse high time is 1/ 1. Since the value accumulated in PPWA_ LW
represents two input high times, A i equals the accumulation of two input pulse high times, and T o /A i
equals 1/ 2. Thus, RATIO = T o /A i * 255/ 2 = 1/ 2 * 255/ 2 = (approximately) 64 = $40.
REF_ ADDR1 points to a synchronization reference value used whenever a link is received that is not
the first link after initialization. Here, it points to LAST_ ACCUM.
Table 5 PPWA Channel Parameter RAM
$FFFF00 0 0 1 1 0 0 0 1 0 0 0 0 0 1 1 1
$FFFF02 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
$FFFF04 X X X X X X X X X X X X X X X X
$FFFF06 X X X X X X X X X X X X X X X X
$FFFF08 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
$FFFF0A X X X X X X X X X X X X X X X X
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REF_ ADDR2 points to a reference value used in calculating the output pulse hightime. Here, it points
to PPWA_ LW.
REF_ ADDR3 points to a synchronization reference value used when the first link service request is ser-viced
after initialization.
The host sequence field bits are initialized to %0x, matches and pulses scheduled. The host service
request bits are set to %11, initialization for the continuous mode.
Load parameter RAM as shown.
8.3 Example C
8.3.1 Description
This example uses the PPWA function with the OC function to divide PPWA input frequency by two.
The PPWA function repeatedly accumulates eight input periods and then generates a link to the OC
function. The OC function scales the accumulated period and then generates the scaled output wave-form.
The PPWA function uses channel 0, and the OC function uses channel 3. Both outputs are 50%
duty cycle.
8.3.2 Initialization
The PPWA function is assigned to channel 0 so that it has higher priority than the OC function. It is set
up for mode 1, accumulate 16-bit periods with links. Its parameters are initialized as followed:
START_ LINK_ CHANNEL is set to 3, since the OC function is on channel 3.
LINK_ CHANNEL_ COUNT is set to 1, since there is one channel in the link block.
CHANNEL_ CONTROL is set to $0B. This sets the TBS field to capture and match TCR1, the PAC field
to detect falling edge for period accumulate, and the PSC field to not force any state.
MAX_ COUNT is the number of periods per accumulation. In this case it is eight.
ACCUM_ RATE determines how often ACCUM will be updated during accumulations. Since a running
accumulation is not desired, this parameter is set to the slowest rate possible, $FF.
The host sequence field bits are set to %01, accumulate 16-bit periods with links. The host service re-quest
bits are set to %10, initialization.
Load parameter RAM as shown.
Table 6 OC Channel Parameter RAM
$FFFF30 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0
$FFFF32 X X X X X X X X X X X X X X X X
$FFFF34 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0
$FFFF36 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0
$FFFF38 X X X X X X X X X X X X X X X X
$FFFF3A X X X X X X X X X X X X X X X X
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The OC function is set up on channel 3 in continuous pulse mode. Its parameters are initialized as fol-lows:
CHANNEL_ CONTROL is set to $8A. This captures and matches TCR1, forces the pin low on a match,
and forces the initial pin level low.
RATIO is an 8-bit fractional number between 0 and $FF used to scale the value indicated by
REF_ ADDR2 to form the output pulse hightime. Here, REF_ ADDR2 points to PPWA_ LW. Thus, for the
input PPWA channel, PPWA_ LW represents a period accumulation, while for the output OC channel,
it represents the unscaled output pulse hightime. The following equation relates the input pulse hightime
accumulation in PPWA_ LW, the desired output period, and RATIO:
T o = 2 * A i * (RATIO/ 255) seconds
In this equation, A i is the accumulation value in PPWA_ LW multiplied by the resolution of the timer for
the input channel, and T o is the period of the output pulse multiplied by the resolution of the timer for
the output channel. The factor of 2 is included since the OC channel scales the value in PPWA_ LW to
be the output pulse hightime instead of the output pulse period. Thus, the scaled output pulse hightime
must be multiplied by two in order to calculate the output pulse period.
Solving this equation for RATIO yields the following:
RATIO = (T o /A i ) * (255/ 2)
In this example, the desired ratio of the output period to the input period is 2/ 1. Since the accumulated
value in PPWA_ LB represents eight input periods, T o /A i = 2/ 1 * 1/ 8 = 1/ 4. Thus, T o /A i * 255/ 2 = 1/ 4 *
255/ 2 = (approximately) 32 = $20.
REF_ ADDR1 points to a synchronization reference value used whenever a link is received that is not
the first link after initialization. Here, it points to LAST_ ACCUM.
REF_ ADDR2 points to a reference value used in calculating the output pulse hightime. Here, it points
to PPWA_ LW.
REF_ ADDR3 points to a synchronization reference value used when the first link service request is ser-viced
after initialization.
The host sequence field bits are initialized to %0x, matches and pulses scheduled. The host service
request bits are set to %11, initialization for the continuous mode.
Load parameter RAM as shown.
Table 7 PPWA Channel Parameter RAM
$FFFF00 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 1
$FFFF02 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
$FFFF04 X X X X X X X X X X X X X X X X
$FFFF06 X X X X X X X X X X X X X X X X
$FFFF08 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
$FFFF0A X X X X X X X X X X X X X X X X
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9 Function Algorithm
The following description is provided as a guide only, to aid understanding of the function. The exact
sequence of operations in microcode may be different from that shown, in order to optimize speed and
code size. TPU microcode source listings for all functions in the TPU function library can be downloaded
from the Motorola Freeware bulletin board. Refer to Using the TPU Function Library and TPU Emulation
Mode (TPUPN00/ D) for detailed instructions regarding downloading and compiling microcode.
The PPWA function consists of five states. For clarity, reference is made in the state descriptions to
internal channel flags 0 and 1. Although the CPU has no access to the channel flags, a description of
their use aids in understanding the following state descriptions.
Flag0 is used as an internal state indicator and is negated in modes 2 and 3 whenever a low-to-high
input transition occurs. It is asserted only in modes 2 and 3 whenever a high-to-low input transition oc-curs.
Flag0 always remains negated in modes 0 and 1.
Flag1 is used as an internal indication in modes 1 and 3 of an overflow of ACCUM. It is asserted when
an overflow of ACCUM occurs and negated when MAX_ COUNT periods are counted.
9.1 STATE 1: INIT
This state is entered as a result of an HSR% 10. The channel latches are configured using
CHANNEL_ CONTROL, ACCUM is initialized to zero, and PIN_ CTRL is copied into
CHANNEL_ CONTROL.
Condition: HSR1, HSR0, M/ TSR, LSR, Pin, Flag0 = 10xxxx
Match Enable: Disable
Configure the channel latches via CHANNEL_ CONTROL
Initialize ACCUM to 0
Clear flag1 and assert flag0
Clear all service requests
9.2 STATE 2: FIRST_ H_ L
This state is entered in modes 0 and 1 for the first high-to-low input transition after Init is executed;
LAST_ ACCUM is updated with the time of the transition. This state is also entered in modes 0 and 1
when a match event occurs for the periodic update of ACCUM while the pin is low. This case happens
only when a match is set up for accumulation at ACCUM_ RATE and the pin goes low prior to the match.
Condition: HSR1, HSR0, M/ TSR, LSR, Pin, Flag0 = 001001
Match Enable: Disable
If (TDL = 1) then {
Update LAST_ ACCUM with ERT
Table 8 OC Channel Parameter RAM
$FFFF30 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0
$FFFF32 X X X X X X X X X X X X X X X X
$FFFF34 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0
$FFFF36 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0
$FFFF38 X X X X X X X X X X X X X X X X
$FFFF3A X X X X X X X X X X X X X X X X
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Setup next match time = ERT + ACCUM_ RATE
Configure pin for high-to-low transition
Clear flag0
}
Else, negate MRL
9.3 STATE 3: HIGH_ TIME_ BEGIN
This state is entered in modes 2 and 3 after a low-to-high input transition. In this state, LAST_ ACCUM
is updated with the time of the transition.
Condition: HSR1, HSR0, M/ TSR, LSR, Pin, Flag0 = 001011
Match Enable: Disable
If (TDL = 1) then {
Update LAST_ ACCUM with ERT
Setup next match time = ERT + ACCUM_ RATE
Configure pin for high-to-low transition
Clear flag0
}
Else, negate MRL
9.4 STATE 4: ACCUM_ LOW_ PIN
This state is entered in all modes after a high-to-low input transition or when a match event occurs for
the periodic update of ACCUM. In this state, the period/ pulse width is accumulated in ACCUM while
PERIOD_ COUNT is less than MAX_ COUNT. PPWA_ UB is incremented for overflows of ACCUM.
When PERIOD_ COUNT is greater than or equal to MAX_ COUNT, PPWA_ LW is updated with ACCUM,
and PERIOD_ COUNT and ACCUM are initialized to zero. An interrupt request is then made to the CPU,
and/ or a link is generated to a block of one or more TPU channels.
Condition: HSR1, HSR0, M/ TSR, LSR, Pin, Flag0 = 00100x
Match Enable: Disable
Update LAST_ ACCUM_ TEMP with LAST_ ACCUM
/* LAST_ ACCUM_ TEMP is a temporary register */
Update LAST_ ACCUM with ERT
If (host sequence bit 1 = 1) then {
Assert flag0
Configure pin for low-to-high transition
Goto UPDATE_ ACCUM
}
SETUP_ ACCUM_ TIME
Setup next match time = ERT + ACCUM_ RATE
Configure pin for high-to-low transition
Clear flag0
Negate MRL
UPDATE_ ACCUM
Update ACCUM = ACCUM + LAST_ ACCUM Ð LAST_ ACCUM_ TEMP
If MRL = 0 then { /* TDL = 1 */
If (ACCUM > 16 bits) then {
Clear flag0, flag1
Clear MRL
Increment PPWA_ UB
If (host sequence bit 0 = 1) then {
Link to channels START_ LINK_ CHANNEL to
[START_ LINK_ CHANNEL + LINK_ CHANNEL_ COUNT Ð 1]
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MOTOROLA TPU Programming Library
24 TPUPN11/ D
}
Else { /* ACCUM £ 16 bits */
PERIOD_ COUNT = PERIOD_ COUNT + 1
Clear MRL, TDL
If (PERIOD_ COUNT ³ MAX_ COUNT) then {
PPWA_ LW = ACCUM
PERIOD_ COUNT = 0
ACCUM = 0
Generate interrupt request
If flag1 = 1 then clear flag1
Else {
Clear flag1
If (host sequence bit 0 = 1) then {
Link to channels START_ LINK_ CHANNEL to
[START_ LINK_ CHANNEL + LINK_ CHANNEL_ COUNT Ð 1
}
}
}
}
Else { /* MRL = 1 */
If TDL = 1 then {
If (ACCUM > 16 bits) then {
Clear flag0, flag1
Clear MRL
Increment PPWA_ UB
If (host sequence bit 0 = 1) then {
Link to channels START_ LINK_ CHANNEL to
[START_ LINK_ CHANNEL + LINK_ CHANNEL_ COUNT Ð 1]
}
}
Else { /* ACCUM £ 16 bits */
PERIOD_ COUNT = PERIOD_ COUNT +1
Clear MRL, TDL
If (PERIOD_ COUNT ³ MAX_ COUNT) then {
PPWA_ LW = ACCUM
PERIOD_ COUNT = 0
Generate interrupt request
If flag1 = 1 then clear flag1
Else {
Clear flag1
If (host sequence bit 0 = 1) then {
Link to channels START_ LINK_ CHANNEL to
[START_ LINK_ CHANNEL + LINK_ CHANNEL_ COUNT Ð 1
}
}
}
}
}
Else { /* TDL = 0 */
If ACCUM > 16 bits) then {
Clear flag0, flag1
Clear MRL
Increment PPWA_ UB
If (host sequence bit 0 = 1) then {
Link to channels START_ LINK_ CHANNEL to
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TPU Programming Library MOTOROLA
TPUPN11/ D 25
[START_ LINK_ CHANNEL + LINK_ CHANNEL_ COUNT -1]
}
}
}
}
9.5 STATE 5: ACCUM_ HIGH_ PIN
This state is entered in all modes when a match event occurs for the periodic update of ACCUM, while
the pin is high. In this state, the period/ pulse width is accumulated in ACCUM, and the next match, which
results in another update of ACCUM, is set up. Also, PPWA_ UB is incremented for overflows of AC-CUM.
If an overflow of ACCUM occurs in this state for modes 1 or 3, a link is generated to a block of
TPU channels.
Condition: HSR1, HSR0, M/ TSR, LSR, Pin, Flag0 = 001010
Match Enable: Disable
Update LAST_ ACCUM_ TEMP with LAST_ ACCUM
/* LAST_ ACCUM_ TEMP is a temporary register */
Update LAST_ ACCUM with ERT
Goto SETUP_ ACCUM_ TIME
The following tables show the PPWA state transitions listing the service request sources and channel
conditions from current state to next state. Figure 12
illustrates the flow of PPWA states in modes 0 and
1; Figure 13
illustrates the flow of PPWA states in modes
2 and 3.
NOTES:
1. Conditions not specified are "don't care."
2. LSR = Link service request
HSR = Host service request
M/ TSR = Either a match or capture (transition) service request occurred (M/ TSR = 1) or neither occurred (M/
TSR = 0).
Table 9 PPWA State Transition Tables
Modes 0 and 1
Current State HSR M/ TSR LSR Pin Flag0 Next State
Any State 10 Ñ Ñ Ñ Ñ S1 Init
S1 Init 00 1 Ñ 0 0 S2 First_ H_ L
S2 First_ H_ L 00
00
1
1
Ñ
Ñ
0
1
0
0
S4 Accum_ Low_ Pin S5 Accum_ High_ Pin
S4 Accum_ Low_ Pin 00
00
1
1
Ñ
Ñ
0
1
0
0
S4 Accum_ Low_ Pin S5 Accum_ High_ Pin
S5 Accum_ High_ Pin 00
00
1
1
Ñ
Ñ
0
1
0
0
S4 Accum_ Low_ Pin S5 Accum_ High_ Pin
Unimplemented Conditions 11
00
Ñ
0
Ñ
1
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
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MOTOROLA TPU Programming Library
26 TPUPN11/ D
NOTES:
1. Conditions not specified are "don't care."
2. LSR = Link service request
HSR = Host service request
M/ TSR = Either an output compare (match) or input capture (transition) service request occurred
(M/ TSR = 1) or neither occurred (M/ TSR = 0).
Table 10 PPWA State Transition Tables
Modes 2 and 3
Current State HSR M/ T LSR Pin Flag0 Next State
Any State 10 Ñ Ñ Ñ Ñ S1 Init
S1 Init 00 1 Ñ 1 0 S3 High_ Time_ Begin
S3 High_ Time_ Begin 00
00
1
1
Ñ
Ñ
1
0
0
0
S5 Accum_ High_ Pin S4 Accum_ Low_ Pin
S4 Accum_ Low_ Pin 00 1 Ñ 1 1 S3 High_ Time_ Begin
S5 Accum_ High_ Pin 00
00
1
1
Ñ
Ñ
0
1
0
0
S4 Accum_ Low_ Pin S5 Accum_ High_ Pin
Unimplemented Conditions 11
00
Ñ
0
Ñ
1
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
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TPU Programming Library MOTOROLA
TPUPN11/ D 27
Figure 12 PPWA Modes 0 and 1 State Flowchart
1050A
KEY:
HSR M/ TSR LSR PIN FLAG0 FLAG1
XX X X X X X
HIGH-TO-LOW TRANSITION
S5 ACCUM _HIGH_ PIN
001x10
S2 FIRST_ H_ L
S1 INIT
10xxxx
001 x 01
FROM ANY STATE
S4 ACCUM_ LOW_ PIN
001x 00
SET FLAG0
MATCH TO UPDATE ACCUM WHILE PIN IS HIGH HIGH-TO-LOW TRANSITION OR MATCH TO UPDATE
ACCUM WHILE PIN IS LOW
HIGH-TO-LOW TRANSITION OR MATCH TO UPDATE
ACCUM WHILE PIN IS LOW
MATCH TO UPDATE ACCUM WHILE PIN
IS HIGH
MATCH TO UPDATE ACCUM WHILE PIN
IS HIGH
HIGH-TO-LOW TRANSITION OR MATCH TO UPDATE
ACCUM WHILE PIN IS LOW
27
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Page 28
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Figure 13 PPWA Modes 2 and 3 State Flowchart
1051A
S4 ACCUM _LOW_ PIN
001x 00
S5 ACCUM _HIGH _PIN
001x10
S3 HIGH_ TIME_ BEGIN
S1 INIT
10xxxx
001x11
FROM ANY STATE
SET FLAG0
MATCH TO UPDATE ACCUM WHILE
PIN IS HIGH
LOW-TO-HIGH TRANSITION
HIGH-TO-LOW TRANSITION
MATCH TO UPDATE ACCUM WHILE
PIN IS HIGH
HIGH-TO-LOW TRANSITION
LOW-TO-HIGH TRANSITION
KEY:
HSR M/ TSR LSR PIN FLAG0 FLAG1
XX X X X X X 28