(**********************************************************************) (* *) (* Function: PWM - Pulse Width Modulation *) (* *) (* Creation Date: Pre 89 From: NEW *) (* *) (* Author: Motorola *) (* *) (* Description: *) (* ------------ *) (* Generate pulse width modulated waveform, CPU supplies period & H.T *) (* 0% and 100% specially handled to be independant of latency issues. *) (* *) (* IMPORTANT NOTES : *) (* 1. PWMHI and PWMPER must be read coherently, note that no *) (* ram access is done in the cycle before they are read. !!! *) (* *) (* Updates: By: Modification: *) (* -------- --- ------------- *) (* 28/Feb/92 JW Cleaned up for inclusion in Library *) (* 11/Apr/93 JL Convert to new syntax & changed unused link *) (* states to End_of_Link. *) (* *) (*--------------------------------------------------------------------*) (* Standard Exits Used:- End_Of_Phase: Y End_Of_Link: N *) (* *) (* External Files %included: NONE. *) (* *) (* CODE SIZE excluding standard exits = 32 LONG WORDS *) (*--------------------------------------------------------------------*) (* *) (* *) (********** This Revision: 2.0 *********) (* *) (* Functionally identical to 68332 TPU ROM of masks D33F, D87M, 2D87M *) (* *) (********** LAST MODIFIED: 11/Apr/93 BY: Jeff Loeliger ********) (* *) (**********************************************************************) (***************************************************************************) (*Motorola reserves the right to make changes without further notice to any*) (*product herein. Motorola makes no warranty, representation or guarantee *) (*regarding the suitability of its products for any particular purpose, nor*) (*does Motorola assume any liability arising out of the application or use *) (*of any product or circuit, and specifically disclaims any and all *) (*liability, including without limitation consequential or incidental *) (*damages. "Typical" parameters can and do vary in different applications. *) (*All operating parameters, including "Typical",must be validated for each *) (*customer application by customer's technical experts. Motorola does not *) (*convey any license under its patent rights nor the rights of others. *) (*Motorola products are not designed, intended, or authorized for use as *) (*components in systems intended for surgical implant into the body, or *) (*other applications intended to support or sustain life, or for any other *) (*application in which the failure of the Motorola product could create a *) (*situation where injury or death may occur. Should Buyer purchase or use *) (*Motorola products for any such unintended or unauthorized application, *) (*Buyer, shall indemnify and hold Motorola and its officers, employees, *) (*subsidiaries, affiliates, and distributors harmless against all claims, *) (*costs, damages, and expenses, and reasonable attorney fees arising out *) (*of, directly or indirectly, any claim of personal injury or death *) (*associated with such unintended or unauthorized use, even if such claim *) (*alleges that Motorola was negligent regarding the design or manufacture *) (*of the part. *) (*Motorola and the Motorola logo are registered trademarks of Motorola Inc.*) (*Motorola is an Equal Opportunity/Affirmative Action Employer. *) (*Copyright Motorola Inc. 1993 *) (***************************************************************************) (* Parameters *) %macro CHANNEL_CONTROL_PWM 'prm0'. %macro OLDRIS 'prm1'. %macro PWMHI 'prm2'. %macro PWMPER 'prm3'. %macro PWMRIS 'prm4'. %macro CHAN_CONT_REG 'p_low'. (**********************************************************************) (* *) (* STATE : Init_pwm *) (* *) (* PRELOAD PARAMETER : CHANNEL CONTROL *) (* *) (* ENTER WHEN : HSR10 is issued *) (* *) (* ACTION : *) (* 1.OLDRIS gets the value of the matched tcr *) (* 2.pin is asserted *) (* 3.Init_cycle is called *) (* 4.Match is generated on OLDRIS + PWMHI *) (* 5.Interrupt request is asserted *) (* *) (**********************************************************************) %entry start_address *; ram p<-@CHANNEL_CONTROL_PWM; disable_match; name = Init_pwm; cond hsr1=1,hsr0=0. Init_pwm : au nil :=<< @CHAN_CONT_REG, ccl; chan clear flag0. chan config := p, enable_mtsr; if N = 0 then goto Normal_L_H. Get_tcr1 : au ert := tcr1; chan neg_tdl, neg_mrl, neg_lsl. Get_tcr2 : au ert := tcr2; chan neg_tdl, neg_mrl, neg_lsl. (**********************************************************************) (* *) (* STATE : Normal_L_H , Normal_100 *) (* *) (* PRELOAD PARAMETER : OLDRIS *) (* *) (* ENTER WHEN : low to high transition occured *) (* (also when executing 100% duty cycle) *) (* *) (* ACTION : *) (* 1.current time is stored is OLDRIS *) (* 2.Init_cycle is called *) (* 3.high_low match is generated on OLDRIS+PWMHI *) (* 4.Interrupt request is asserted *) (* *) (**********************************************************************) %entry start_address *; ram p<-@OLDRIS; name = normal_l_h; cond hsr1=0,hsr0=0,m/tsr=1,lsr=0,pin=1,flag0=x. Normal_L_H : au diob := ert; ram diob -> @OLDRIS. call_init_cycle : call Init_cycle, flush. (* on return a = PWMHI, sr = OLDRIS diob = PWMPER *) au ert := a + sr; chan write_mer, neg_mrl,pac := high_low; chan cir; end. (**********************************************************************) (* *) (* PROCEDURE : Init_cycle *) (* *) (* CALLED BY : *) (* *) (* ACTION : *) (* 1.PWMHI and PWMPER are read coherently *) (* 2.PWMRIS := OLDRIS + PWMPER *) (* #3.If PWMHI = 0 then *) (* flag0 is chan set *) (* no_change match is generated on OLDRIS+ PWMPER *) (* interrupt request is asserted *) (* pin is cleared *) (* *) (* 3.If PWMHI >= PWMPER then *) (* flag0 is chan set *) (* no_change match is generated on OLDRIS+ PWMPER *) (* interrupt request is asserted *) (* pin is chan set *) (* *) (* *) (* PARAMETERS & REGISTERS : *) (* *) (* ON ENTRY *) (* diob - OLDRIS *) (* a - UNKNOWN *) (* sr - UNKNOWN *) (* ON EXIT *) (* diob - PWMPER *) (* a - PWMHI *) (* sr - OLDRIS *) (* *) (* NOTE : The coherency of PWMPER and PWMHI reading is guaranteed *) (* by the call to Init_cycle wich is always done with a *) (* FLUSH!!!! *) (* *) (**********************************************************************) Init_cycle : au sr := diob; ram p <- @PWMHI. au a := p, ccl; ram diob <- @PWMPER. Check_duty_cycle : if LOW_SAME = 1 then goto duty_0. au p := diob + sr; ram p -> @PWMRIS. au nil := diob - a, ccl. if LOW_SAME = 1 then goto duty_100, flush. return, flush; chan clear flag0. duty_0 : au ert := sr + diob; chan write_mer, neg_mrl,pin := low, pac := no_change; chan set flag0; chan cir; end. duty_100 : au ert := sr + diob; chan write_mer,neg_mrl,pin := high, pac := no_change; chan set flag0; chan cir; end. (**********************************************************************) (* *) (* STATE : Immed_H *) (* *) (* PRELOAD PARAMETER : OLDRIS *) (* *) (* ENTER WHEN : HSR11 is issued and pin is high *) (* *) (* ACTION : *) (* 1.Init_cycle is called *) (* 2.high_low match is generated on OLDRIS+PWMHI *) (* 3.Interrupt request is asserted *) (* *) (**********************************************************************) %entry start_address *; ram diob<-@OLDRIS; disable_match; name = immed_h; cond hsr1=0,hsr0=1,m/tsr=x,flag0=x,pin=1. if MRL = 1 then goto Normal_L_H, flush. (* Match pending? *) goto call_init_cycle, flush. (**********************************************************************) (* *) (* STATE : Immed_L *) (* *) (* PRELOAD PARAMETER : OLDRIS *) (* *) (* ENTER WHEN : HSR11 is issued and pin is low *) (* *) (* ACTION : *) (* 1.Init_cycle is called *) (* 2.low to high match is generated on OLDRIS+PWMPER *) (* 5.Interrupt request is asserted *) (* *) (**********************************************************************) %entry start_address * ; ram diob<-@OLDRIS; disable_match; name = immed_l; cond hsr1=0,hsr0=1,m/tsr=x,flag0=x,pin=0. if MRL = 0 then goto Immed_L, flush. (* Match pending? *) if flag0 = 0 then goto Immed_L, flush. (* Normal PWM? *) (* Else, match pending and 0% or 100 % PWM so fall through *) (**********************************************************************) (* *) (* STATE : Normal_0 *) (* *) (* PRELOAD PARAMETER : NONE *) (* *) (* ENTER WHEN : executing 0% duty cycle *) (* (match occured and flag0 is set) *) (* *) (* ACTION : *) (* 1.match time is stored into OLDRIS *) (* 2.Init_cycle is called *) (* 3.If not in level mode (init_cycle returns) *) (* low to high match is generated on OLDRIS+PWMPER *) (* 5.Interrupt request is asserted *) (* *) (**********************************************************************) %entry start_address Normal_0; name = normal_0; cond hsr1=0,hsr0=0,m/tsr=1,flag0=1,pin=0,lsr=0. Normal_0 : au diob := ert; ram diob -> @OLDRIS. Immed_L : (* call init_cycle, match on oldris + pwmper *) Call Init_cycle, flush. au ert := sr + diob; chan write_mer, neg_mrl,pac := low_high; chan cir; end. (**********************************************************************) (* *) (* STATE : Normal_H_L *) (* *) (* PRELOAD PARAMETER : PWMRIS *) (* *) (* ENTER WHEN : high to low transition ocurred *) (* *) (* ACTION : *) (* 1.low to high transition is generated on PWMRIS *) (* *) (**********************************************************************) %entry start_address Normal_H_L; ram p<-@PWMRIS; name = normal_h_l; cond hsr1=0,hsr0=0,m/tsr=1,lsr=0,pin=0,flag0=0. Normal_H_L : au ert := p; chan write_mer, neg_mrl,pac := low_high; end. (**********************************************************************) (* UNUSED ENTRIES - execute an end *) (**********************************************************************) %entry start_address End_of_Link; name = pwm_undef; cond hsr1=0,hsr0=0,lsr = 1. %entry start_address End_of_phase; name = pwm_undef; cond hsr1=1,hsr0=1.